Due to the rapid development of LSI and VLSI, the process feature size of the chip has reached the deep sub-micron level (0.15μm), the chip size has reached more than 20mm×20 mm, and the number of I/Os has exceeded 1,000. However, the chip package has become one of the big problems, people try to package it directly on the PCB. There are two commonly used packaging methods: one is the COB method, and the other is the flip-chip (C4) method. The bare chip (Bare Chip) that applies the COB method is also called the COB chip, and the latter is called the Flip Chip, or F·C for short. The structure of the two is different, which is introduced as follows.
The welding area and the chip body are on the same plane, and the periphery of the welding area is evenly distributed. The minimum area of the welding area is 90μm×90μm, and the minimum distance is 100μm. Since the COB chip welding area is distributed around the periphery, the number of I/O growth is limited, especially when it uses wire bonding (bonding machine) to connect the welding area to the PCB pad. Therefore, the PCB pad should be There is a corresponding number of pads, and they are also arranged on the periphery, in order to adapt to it. Therefore, the difficulty of the PCB manufacturing process is relatively increased. In addition, the heat dissipation of the COB is also difficult.
Usually, COB is only suitable for IC chips with low power consumption (0.5～1W). At present, COB chips can be customized, and the general price is only half of QFP.
The F·C chip was first developed by IBM in the United States in the 1960s. The difference between it and COB is that the solder joints are arranged in an area array on the chip, and the solder area is made of a bump structure. The outer layer of the bump is Sn/Pb solder, so the F·C is placed on the PCB when soldering. And can adopt the SMT method to realize welding. This method of welding has the following names:
·Especially F·C is placed on the PCB;
·Controlled Collapsed Chip Connection (C4 for short).
Generally, the pitch of F·C solder joints is 0.4mm or 0.5mm, and the bumps are arranged in an area array. The number of bumps was 102 at first, and 402 has been achieved.
F·C bump production is the key. The usual method is to first cover the barrier metal layer (protective layer) on the aluminum electrode of the chip, taking into account the corrosion reaction of the solder (Sn-Pb) and aluminum and the low bonding strength According to the different methods of each company, the protective layer of different materials is plated on the aluminum electrode, and then the metal Cu or Ni with good solder wettability is vapor-deposited on the electrode in turn, and finally, Sn-Pb solder is coated Make bump-shaped electrodes.
The above information is provided by COB chip supplier.